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Cyrix 6x86
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Microprocessor
CAPTION: 6x86/MII
Cyrix 6x86-P166.jpg
A Cyrix 6x86-P166 processor
General information
Launched
* 6x86 - Oct 1995
* 6x86L - Jan 1997
* 6x86MX - Jun 1997
* MII - May 1998
Discontinued
* 6x86 - Jun 1999
* 6x86L - Jun 1999
* 6x86MX - May 1998
* MII - Early 2000s
Marketed by
* Cyrix
* IBM
* SGS-Thomson
* VIA
Common manufacturer(s)
* IBM
* SGS-Thomson
* National Semiconductor
Performance
Max. CPU clock rate 80 MHz to 333 MHz
FSB speeds 40 MHz to 100 MHz
Cache
L1 cache
* 16 KB (6x86/L)
* 64 KB (6x86MX / MII)
Architecture and classification
Microarchitecture 6x86
Instruction set IA-32/x86
Physical specifications
Transistors
* 4.3M 500 nm
Cores
* 1
Socket(s)
* Socket 7
* Super Socket 7
Products, models, variants
Core name(s)
* M1
* M1L (Low voltage)
* M1R (3M to 5M)
* MII (MMX)
Variant(s)
* 6x86, 6x86L, 6x86MX
History
Predecessor Cyrix 5x86
Successor Cyrix III
The Cyrix 6x86 is a line of sixth-generation, 32-bit x86
microprocessors designed and released by Cyrix in 1995. Cyrix, being a
fabless company, had the chips manufactured by IBM and
SGS-Thomson.^[1]^[2] The 6x86 was made as a direct competitor to
Intel's Pentium microprocessor line, and was pin compatible. During the
6x86's development, the majority of applications (office software as
well as games) performed almost entirely integer operations. The
designers foresaw that future applications would most likely maintain
this instruction focus. So, to optimize the chip's performance for what
they believed to be the most likely application of the CPU, the integer
execution resources received most of the transistor budget. This would
later prove to be a strategic mistake, as the popularity of the P5
Pentium caused many software developers to hand-optimize code in
assembly language, to take advantage of the P5 Pentium's tightly
pipelined and lower latency FPU. For example, the highly anticipated
first-person shooter Quake used highly optimized assembly code designed
almost entirely around the P5 Pentium's FPU. As a result, the P5
Pentium significantly outperformed other CPUs in the
game.^[3]^[4]^[5]^[6]
[ ]
Contents
* 1 History
* 2 Architecture
* 3 Performance
* 4 Models & Variants
+ 4.1 6x86
+ 4.2 6x86L
+ 4.3 6x86MX / MII
+ 4.4 Model Table
* 5 References
* 6 Further reading
* 7 External links
History[edit]
The 6x86, previously under the codename "M1" was announced by Cyrix in
October of 1995.^[2]^[7]^[8]^[9]^[10] On release only the 100 MHz
(P120+) version was available, but a 120 MHz (P150+) version was
planned for mid-1995 with a 133 MHz (P166+) model later. The 100 MHz
(P120+) 6x86 was available to OEMs for a price of $450 per chip in bulk
quantities.^[11]
In mid February of 1996 Cyrix announced the P166+, P150+, and P133+ to
be added to the 6x86 model line.^[12] IBM, who produced the chips, also
announced they will be selling their own versions of the chips.^[13]
The 6x86 P200+ was planned for the end of 1996,^[12] and ended up being
released in June.^[14]
The M2 (6x86MX) was first announced to be in development in mid 1996.
It would have MMX and 32-bit optimization. The M2 would also have some
of the same features as the Intel Pentium Pro such as register
renaming, out-of-order completion, and speculative execution.
Additionally it would have 64 KB of cache over the original 6x86 and
Pentium Pro's 16 KB.^[15] In March of 1997 when asked about when the M2
line of processors would begin shipping, Cyrix UK managing director
Brendan Sherry stated, "I've read it's going to be May but we've said
late Q2 all along and I'm pretty sure we'll make that."^[16]
The 6x86L was first released in January of 1997 to address the heat
issues with the original 6x86 line.^[17] The 6x86L had a lower V-core
voltage and required a split powerplane voltage regulator.
Later by the end of May 1997 on the 27th, Cyrix said they would
announce details of the new chip line (6x86MX) the day before Computex
in June of 1997.^[18] For the low end of the series, the PR166 6x86MX
was available for $190 with higher end PR200 and PR233 versions
available for $240 and $320.^[19]^[20] IBM being the producer of
Cyrix's chips, would also sell their own version. Cyrix hoped to ship
tens of thousands within June of 1997 with up to 1 million by the end
of the year. Cyrix also expected to release a 266 MHz chip by the end
of the 1997 and a 300 MHz in the first quarter of 1998.^[21] They had
slightly better floating point performance, which cut adding and
multiply times by a third, but it was still slower than the Intel
Pentium. The M2 also had full MMX instructions, 64KB of cache over the
original 16KB, and had a lower core voltage of 2.5V over 3.3V of the
original 6x86 line.^[22]^[23]
National Semiconductor acquired Cyrix in July of 1997.^[24]^[25]^[26]
National Semiconductor was not interested in high performance
processors but rather system on a chip devices, and wanted to shift the
focus of Cyrix to the MediaGX line.^[27]
In January of 1998 National Semiconductors produced a 6x86MX processor
on a .25 micron process technology. This reduced the chip size from 150
millimeters squared to 88.^[28]
In September of 1998 IBM's licensing partnership with Cyrix was said to
be ended by National Semiconductors.^[29]^[30] This was due to National
wanting to increase production of Cyrix chips in their own facilities,
and because having IBM produce Cyrix's chips was causing issues such as
profit losses due to IBM frequently pricing their versions of Cyrix's
chips lower.^[31] National would be paying $50-55 million to IBM to end
the partnership, which would end the following April. National would
then be moving chip production to their own facility in South Portland,
Maine.^[32]^[33]
The Cyrix MII was released in May of 1998. These chips were not
exciting like people had hoped, as they were just a rebranding of the
6x86MX.^[34] In December these chips cost $80 for a MII-333, $59 for a
MII-300, $55 for a MII-266, and $48 for a MII-233.^[35]
In May 1999 National Semiconductor decided to leave the PC chip market
due to significant losses, and put the Cyrix CPU division up for
sale.^[36]^[24]
VIA bought the Cyrix line in June of 1999, and ended the development of
high performance processors. The MII-433GP would be the last processor
produced by Cyrix. ^[37] Additionally after VIA's acquisition, the
6x86/L was discontinued, but the 6x86MX/MII line continued to be sold
by VIA. ^[38] ^[39]
VIA would continue to produce the MII throughout the early 2000s. It
was expected to be discontinued when the VIA Cyrix MII was
released.^[40] However, the MII was still available for sale until
mid/late 2003, being shown on VIA's website as a product until October,
and it still saw use in devices such as network computers.^[41]^[42]
Architecture[edit]
A simplistic block diagram of the Cyrix 6x86 microarchitecture
The 6x86 is superscalar and superpipelined and performs register
renaming, speculative execution, out-of-order execution, and data
dependency removal.^[43] However, it continued to use native x86
execution and ordinary microcode only, like Centaur's Winchip, unlike
competitors Intel and AMD which introduced the method of dynamic
translation to micro-operations with Pentium Pro and K5. The 6x86 is
socket-compatible with the Intel P54C Pentium, and was offered in six
performance levels: PR 90+, PR 120+, PR 133+, PR 150+, PR 166+ and PR
200+. These performance levels do not map to the clock speed of the
chip itself (for example, a PR 133+ ran at 110 MHz, a PR 166+ ran at
133 MHz, etc.).
With regard to internal caches, it has a 16-KB primary cache and a
fully associative 256-byte instruction line cache is included alongside
the primary cache, which functions as the primary instruction
cache.^[43]
The 6x86 and 6x86L were not completely compatible with the Intel P5
Pentium instruction set and is not multi-processor capable. For this
reason, the chip identified itself as an 80486 and disabled the CPUID
instruction by default. CPUID support could be enabled by first
enabling extended CCR registers then setting bit 7 in CCR4. The lack of
full P5 Pentium compatibility caused problems with some applications
because programmers had begun to use P5 Pentium-specific instructions.
Some companies released patches for their products to make them
function on the 6x86.
Compatibility with the Pentium was improved in the 6x86MX, by adding a
Time Stamp Counter to support the P5 Pentium's RDTSC instruction.^[44]
Support for the Pentium Pro's CMOVcc instructions were also added.^[44]
Performance[edit]
Similarly to AMD with their K5 and early K6 processors, Cyrix used a PR
rating (Performance Rating) to relate their performance to the Intel P5
Pentium (pre-P55C), as the 6x86's higher per-clock performance relative
to a P5 Pentium could be quantified against a higher-clocked Pentium
part. For example, a 133 MHz 6x86 will match or outperform a P5 Pentium
at 166 MHz, and as a result Cyrix could market the 133 MHz chip as
being a P5 Pentium 166's equal. However, the PR rating was not an
entirely truthful representation of the 6x86's performance.^[45]
While the 6x86's integer performance was significantly higher than P5
Pentium's, its floating point performance was more mediocre--between 2
and 4 times the performance of the 486 FPU per clock cycle (depending
on the operation and precision). The FPU in the 6x86 was largely the
same circuitry that was developed for Cyrix's earlier high performance
8087/80287/80387-compatible coprocessors, which was very fast for its
time--the Cyrix FPU was much faster than the 80387, and even the 80486
FPU. However, it was still considerably slower than the new and
completely redesigned P5 Pentium and P6 Pentium Pro-Pentium III FPUs.
One of the main features of the P5/P6 FPUs is that they supported
interleaving of FPU and integer instructions in their design, which
Cyrix chips did not integrate. This caused very poor performance with
Cyrix CPUs on games and software that took advantage of this.^[46]^[47]
Therefore, despite being very fast clock by clock, the 6x86 and MII
were forced to compete at the low-end of the market as AMD K6 and Intel
P6 Pentium II were always ahead on clock speed. The 6x86's and MII's
old generation "486 class" floating point unit combined with an integer
section that was at best on-par with the newer P6 and K6 chips meant
that Cyrix could no longer compete in performance.
Models & Variants[edit]
6x86[edit]
The 6x86 (codename M1) was released by Cyrix in 1996. The first
generation of 6x86 had heat problems. This was primarily caused by
their higher heat output than other x86 CPUs of the day and, as such,
computer builders sometimes did not equip them with adequate cooling.
The CPUs topped out at around 25 W heat output (like the AMD K6),
whereas the P5 Pentium produced around 15 W of waste heat at its peak.
However, both numbers would be a fraction of the heat generated by many
high performance processors, some years later. Shortly after the
original M1, the M1R was released. The M1R was a switch from
SGS-Thomson 3M process to IBM 5M process.
* Early Cyrix 6x86 (M1) die shot
6x86L[edit]
The 6x86L (codename M1L) was later released by Cyrix to address heat
issues; the L standing for low-power. Improved manufacturing
technologies permitted usage of a lower Vcore. Just like the Pentium
MMX, the 6x86L required a split powerplane voltage regulator with
separate voltages for I/O and CPU core.
* Cyrix 6x86L (M1L) die shot
6x86MX / MII[edit]
Another release of the 6x86, the 6x86MX, added MMX compatibility along
with the EMMI instruction set, improved compatibility with the Pentium
and Pentium Pro by adding a Time Stamp Counter and CMOVcc instructions
respectively, and quadrupled the primary cache size to 64 KB. The
256-byte instruction line cache can be turned into a scratchpad cache
to provide support for multimedia operations.^[44] Later revisions of
this chip were renamed MII, to better compete with the Pentium II
processor. Unfortunately, 6x86MX / MII was late to market, and couldn't
scale well in clock speed with the manufacturing processes used at the
time.
* Cyrix 6x86MX (M2) die shot
Model Table[edit]
Images Model Core name Process size
(mm)
Die area
(mm2)
Number of transistors
(millions)
Socket(s) Package Core Voltage TDP (W) Clock speed Bus Speed L1 Cache
Price (USD) Launch
* KL Cyrix 6x86.jpg
* Cyrix 6x86-P166.jpg
PR90+ M1 0,65 394 3.0 Socket 7 CPGA 3.3 15.5 80 MHz 40 MHz 16 KB $84
Nov 1995
PR120+ M1 0,65 394 3.0 Socket 7 CPGA 3.3 ? 100 MHz 50 MHz 16 KB $450
Oct 1995
PR133+ M1R 0,65 225 3.0 Socket 7 CPGA 3.3 19.1 110 MHz 55 MHz 16 KB
$326 2-5-1996
PR150+ M1R 0,65 225 3.0 Socket 7 CPGA 3.3/3.52 20.1 120 MHz 60 MHz 16
KB $451 2-5-1996
PR166+ M1R 0,65 225 3.0 Socket 7 CPGA 3.3/3.52 21.8 133 MHz 66 MHz 16
KB $621 2-5-1996
PR200+ M1R 0,44 ? 3.0 Socket 7 CPGA 3.52 17.13 150 MHz 75 MHz 16 KB
$499 6-6-1996
* Cyrix6x86L-PR166.jpg
* KL Cyrix 6x86L.jpg
L-PR120+ M1L 0,35 169 3.0 Socket 7 CPGA 2.8/3.3 ? 100 MHz 50 MHz 16 KB
? Jan-1997
L-PR133+ M1L 0,35 169 3.0 Socket 7 CPGA 2.8/3.3 ? 110 MHz 55 MHz 16 KB
? Feb-1997
L-PR150+ M1L 0,35 169 3.0 Socket 7 CPGA 2.8/3.3 ? 120 MHz 60 MHz 16 KB
? Mar-1997
L-PR166+ M1L 0,35 169 3.0 Socket 7 CPGA 2.8/3.3 15.98 133 MHz 66 MHz 16
KB ? Apr-1997
L-PR200+ M1L 0,35 169 3.0 Socket 7 CPGA 2.8/3.3 17.13 150 MHz 75 MHz 16
KB ? Apr-1997
* KL Cyrix 6x86MX.jpg
* Ic-photo-Cyrix--6x86MX-PR233--(6x86MX-CPU).png
PR166-MMX MII 0,35 197 6.0 Socket 7 CPGA 2.9/3.3 ?
?
133 MHz
150 MHz
66 MHz
60 MHz
64 KB $190
?
5-30-97
Q2 1998
PR200-MMX MII 0,35 (IBM)
0,30 (NS)
197
156
6.0 Socket 7 CPGA 2.9/3.3 ?
?
150 MHz
166 MHz
75 MHz
66 MHz
64 KB $240
?
5-30-97
Q2 1998
PR233-MMX MII 0,35 (IBM)
0,30 (NS)
197
156
6.0 Socket 7 CPGA 2.9/3.3 ?
?
188 MHz
200 MHz
75 MHz
66 MHz
64 KB $320
?
5-30-97
Q2 1998
PR266-MMX MII 0,35 (IBM)
0,30 (NS)
197
156
6.0 Socket 7 CPGA 2.9/3.3 ? 208 MHz 83 MHz 64 KB $180
?
3-19-98
Q2 1998
* Cyrix-m2-233gp 75x2.5.jpg
* KL Cyrix MII-333.jpg
* Cyrix M II-433GP - 300MHz CPU 1998 front.jpg
MII-300-MMX MII 0,30
0,25
156
88
6.0 Super 7 CPGA 2.9/3.3 ?
?
233 MHz
225 MHz
66 MHz
75 MHz
64 KB $180
?
4-14-98
Q1 1999
MII-333-MMX MII 0,30
0,25
156
88
6.0 Super 7 CPGA 2.9/3.3 ?
?
250 MHz 100 MHz
83 MHz
64 KB $180
?
6-15-98
Mar-1999
MII-350-MMX MII 0,25 88 6.0 Super 7 CPGA 2.9/3.3 ? 270 MHz
250 MHz
90 MHz
83 MHz
64 KB ?
?
?
?
MII-366-MMX MII 0,25 88 6.0 Super 7 CPGA 2.9/3.3 ? 250 MHz 100 MHz 64
KB ? Mar-1999
MII-400-MMX MII 0,18 65 6.0 Super 7 CPGA 2.2/3.3 ? 285 MHz 95 MHz 64 KB
? Jun-1999
MII-433-MMX MII 0,18 65 6.0 Super 7 CPGA 2.2/3.3 ? 300 MHz 100 MHz 64
KB ? Jun-1999
? SGS-Thomson 6x86 Models
ST6x86P90+HS M1 0,65 394 3.0 Socket 7 CPGA 3.52 17.39 80 MHz 40 MHz 16
KB ? ?
ST6x86P120+HS M1 0,65 394 3.0 Socket 7 CPGA 3.52 19.98 100 MHz 50 MHz
16 KB ? 2-5-1996
ST6x86P133+HS M1 0,65 394 3.0 Socket 7 CPGA 3.52 21.46 110 MHz 55 MHz
16 KB ? 2-5-1996
ST6x86P150+HS M1 0,65 225 3.0 Socket 7 CPGA 3.52 ? 120 MHz 60 MHz 16 KB
? 2-5-1996
ST6x86P166+HS M1 0,65 225 3.0 Socket 7 CPGA 3.52 ? 133 MHz 66 MHz 16 KB
? 2-5-1996
ST6x86P200+HS M1 0,44 ? 3.0 Socket 7 CPGA 3.52 ? 150 MHz 75 MHz 16 KB ?
?
* IBM 6x86 P150+ CPU.jpg
* KL IBM 6x86 P166+ Cyrix.jpg
IBM 6x86 Models
[2V2100GB] M1 0,65 394 3.0 Socket 7 CPGA 3.3 ? 80 MHz 40 MHz 16 KB ? ?
[2V2P120GC] M1 0,65 394 3.0 Socket 7 CPGA 3.3 ? 100 MHz 50 MHz 16 KB ?
?
[2V2120GB] M1R 0,65 394 3.0 Socket 7 CPGA 3.33 ? 100 MHz 50 MHz 16 KB ?
?
[2V2P150GE] M1R 0,65 225 3.0 Socket 7 CPGA 3.3/3.52 ? 120 MHz 60 MHz 16
KB ? 2-5-1996
[2V2P166GE] M1R 0,65 225 3.0 Socket 7 CPGA 3.3/3.52 21.8 133 MHz 66 MHz
16 KB ? 2-5-1996
[2V7P200GE] M1R 0,44 ? 3.0 Socket 7 CPGA 3.52 14 150 MHz 75 MHz 16 KB ?
2-5-1996
* KL IBM 6x86L Cyrix.jpg
[2VAP120GB] M1L 0,35 169 3.0 Socket 7 CPGA 2.8 ? 100 MHz 50 MHz 16 KB ?
?
[2VAP150GB] M1L 0,35 169 3.0 Socket 7 CPGA 2.8 ? 120 MHz 60 MHz 16 KB ?
?
[2VAP166GB] M1L 0,35 169 3.0 Socket 7 CPGA 2.8 ? 133 MHz 66 MHz 16 KB ?
?
[2VAP200GB] M1L 0,35 169 3.0 Socket 7 CPGA 2.8 ? 150 MHz 75 MHz 16 KB ?
?
* KL IBM 6x86MX.jpg
* Cyrix IBM CPU 6x86MX PR200 top.jpg
* IBM PR300.jpg
* [AVAPR166GB]
* ?
MII 0,35 197 6.0 Socket 7 CPGA 2.9/3.3 ? 133 MHz
150 MHz
66 MHz
60 MHz
64 KB $202 5-30-97
* [BVAPR200GB]
* [AVAPR200GA]
MII 0,35
0,30
? 6.0 Socket 7 CPGA 2.9/3.3 ?
?
150 MHz
166 MHz
75 MHz
66 MHz
64 KB $369
?
5-30-97
Q2 1998
* [BVAPR233GC]
* [AVAPR233GB]
* [BVAPR233GD]
MII 0,35
0,30
? 6.0 Socket 7 CPGA 2.9/3.3 ?
? ?
166 MHz
188 MHz 200 MHz
83 MHz
75 MHz 66 MHz
64 KB $477
? ?
5-30-97
Q2 1998
[BVAPR266GE] MII 0,35
0,30
? 6.0 Socket 7 CPGA 2.9/3.3 ? 208 MHz 83 MHz 64 KB ? 3-19-98
Q2 1998
* [CVAPR300GF]
* [DVAPR300GF]
MII 0,25 119 6.0 Super 7 CPGA 2.9/3.3 ?
?
225 MHz
233 MHz
75 MHz
66 MHz
64 KB $217
?
3-19-98
* [CVAPR333GF]
* ?
MII 0,25 119 6.0 Super 7 CPGA 2.9/3.3 ?
?
250 MHz
263 MHz
83 MHz
75 MHz
64 KB $299
?
3-19-98
?
? - Missing information
Information From:
* https://www.pchardwarelinks.com/586.htm
* https://www.cpu-world.com/CPUs/6x86/
* https://www.x86-guide.net/
* http://www.cpu-galerie.de/
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the PC Chip Business". The New York Times. Retrieved April 11,
2022.
37. ^ Carroll, Mark (June 30, 1999). "Via Technologies to acquire
Cyrix". EETimes. Retrieved April 8, 2022.
38. ^ Mueller, Scott (2003). "Cyrix/IBM 6x86 (M1) and 6x86MX (MII)".
Upgrading and Repairing PCs. Que. pp. 175-176. ISBN 9780789729743.
Retrieved April 8, 2022.
39. ^ Hachman, Mark (November 17, 1999). "Via Technologies' Samuel
microprocess or to anchor 2000 chip lineup". EETimes. Retrieved
April 26, 2022.
40. ^ Hachman, Mark (November 17, 1999). "Via Technologies' Samuel
microprocessor to anchor 2000 chip lineup". EETimes. Retrieved
April 26, 2022.
41. ^ "Ellison's Net computer gets a pricey accessory". CNet. January
2, 2002. Retrieved April 26, 2022.
42. ^ "VIA Cyrix(R) MII(TM)". June 25, 2003. Retrieved April 26, 2022.
43. ^ ^a ^b "Cyrix M1 datasheet" (PDF). Cyrix.
44. ^ ^a ^b ^c "IBM 6x86MX datasheet" (PDF).
45. ^ Phillips, Jon (July 2000). "The Pre-Fab Debate Continues".
Maximum PC. Vol. 5, no. 7. Future US, Inc. p. 16. ISSN 1522-4279.
Retrieved April 5, 2022.
46. ^ Mury, John. "CPU Considerations; Cyrix". NiNe's Rendition Quake
Workshop. Retrieved April 7, 2022.
47. ^ Hsieh, Paul (September 7, 1999). "6th Generation CPU Comparisons;
The Cyrix 6x86MX". Retrieved April 7, 2022.
Further reading[edit]
* Gwennap, Linley (October 25, 1993). "Cyrix Describes Pentium
Competitor" Microprocessor Report.
* Gwennap, Linley (December 5, 1994). "Cyrix M1 Design Tapes Out".
Microprocessor Report.
* Gwennap, Linley (June 2, 1997). "Cyrix 6x68MX Outperforms AMD K6".
Microprocessor Report.
* Slater, Michael (February 12, 1996). "Cyrix, IBM Push 6x86 to 133
MHz". Microprocessor Report.
* Slater, Michael (October 28, 1996). "Cyrix Doubles x86 Performance
with M2". Microprocessor Report.
External links[edit]
* Cyrix 6x86 ("M1") at PCGuide at the Wayback Machine (archived June
22, 2017)
* Cyrix 6x86 ("M1") at PCGuide
* cpu-collection.de Cyrix 6x86 processor images and descriptions
* Paul Hsieh's 6th Generation x86 CPU Comparison in-depth analysis of
6th generation x86 CPUs, including the 6x86MX.
* Cyrix M1 stats at Sandpile.org
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